The present invention relates to a semiconductor storage unit and a method of manufacturing the same.
Recently, a semiconductor storage unit has been highly integrated and each element included in the semiconductor storage unit has a minute size. Consequently, the elements are arranged quite closely. For instance, in manufacturing processes for DRAM having a general stack-type memory cell structure, an active region, an element- isolation region, a word line (a gate electrode), a bit line, and a memory cell capacitor are formed on a semiconductor substrate sequentially. A method of manufacturing a conventional semiconductor storage unit will be explained with reference to FIGS. 20-23 as an example of a manufacturing process for DRAM having a stack-type memory cell structure as follows.
First, in processes shown in FIGS. 20(a) and (b), a laminated film 302 of a silicon nitride film and a silicon oxide film is formed on a semiconductor substrate 301, and using a photoresist 303 a part of the laminated film 304 and a part of the semiconductor substrate 305 are removed by photoetching, thus forming grooves 306.
As next steps, in processes shown in FIGS. 20(c), (d), and (e), after depositing a CVD silicon oxide film 307, a part of the laminated film 304 and a part of the silicon oxide film 307 are removed by polishing to flatten the whole surface and to leave a filled-in film 310 within the grooves 309. Then, the whole laminated film 308 and a part of the filled-in film 310 are removed by wet etching to leave the filled-in film 311 and to expose a surface 312 of the semiconductor substrate.
In processes shown in FIGS. 21(a) and (b), a gate oxide film 313 and a polysilicon film 314 containing impurities are formed sequentially, and then a gate electrode (a word line) 316 is formed by photoetching using a photoresist 315. As a next step, in a process shown in FIG. 21(c), an impurity-diffusion layer 318 is formed by ion implantation 317.
In processes shown in FIG. 21(d) and FIG. 22(a), a CVD silicon oxide film 319 is deposited and flattened, and then a contact hole 321 is formed by photoetching using a photoresist 320. As a next step, in a process shown in FIG. 22(b), after depositing a laminated film 322 of a tungsten silicide film and a polysilicon film containing impurities, a bit line 322 is formed by photoetching.
In processes shown in FIGS. 22(c) and (d), a CVD silicon oxide film 323 is deposited and flattened, and then a contact hole 325 is formed by photoetching using a photoresist 324. As next steps, in processes shown in FIGS. 23(a) and (b), a polysilicon film 326 containing impurities is deposited and a charge-storage electrode 328 is formed by photoetching using a photoresist 327.
Then, in a process shown in FIG. 23(c), a capacity insulating film 329 formed of a laminated film of a silicon oxide film and a silicon nitride film and a polysilicon film 330 containing impurities are formed sequentially, and a plate electrode 330 is then formed by photoetching.
However, in the conventional semiconductor storage unit described above, all the conductive layers of the gate electrode 316, the bit line 322, the charge-storage electrode 328, and the plate electrode 330 are provided on the semiconductor substrate. Therefore, there has been a possibility that a short-circuit occurs easily between the conductive layers when the width of an isolation region between elements and the thickness of an insulating film are decreased according to the higher integration.
Further, in order to secure the insulation between upper and lower conductive layers, it is necessary to increase the thickness of an insulating film between the upper and lower conductive layers. Consequently, the depth of a connection hole for connecting a conductive layer of an upper layer and the semiconductor substrate is increased and therefore the aspect ratio increases, thus deteriorating the covering condition inside the connection hole in the conductive layers. As a result, there has been a problem that poor electric connection occurs inside the connection hole.
The present invention aims to solve the problems described above. It is an object of the present invention to provide a semiconductor storage unit at a low manufacturing cost by reducing the number of manufacturing processes, in which the formation of a gate electrode within a semiconductor substrate reduces the occurrence of a short circuit between conductive layers and therefore provides an excellent electric connection in a connection hole between the semiconductor substrate and conductive layers, and a method of manufacturing the same.
In order to attain the object described above, a semiconductor storage unit of the present invention comprises a semiconductor substrate, an impurity-diffusion layer, an insulating film, a bit line of a conductive film, a charge-storage electrode of a conductive film, and a gate electrode of a conductive film, which are formed on the semiconductor substrate. The impurity-diffusion layer has a reverse conductive type as compared to that of the semiconductor substrate and is formed on the semiconductor substrate. In the semiconductor storage unit, the bit line and the charge-storage electrode are connected to the surface of the semiconductor substrate. A plurality of openings are formed in the semiconductor substrate. A filled-in layer of an insulating film is formed within the openings and the gate electrode is formed within the filled-in layer.
According to the semiconductor storage unit described above, the gate electrode is provided within the semiconductor substrate. Therefore, the short-circuit between the gate electrode and the other conductive layers does not occur easily, thus improving the reliability of the semiconductor storage unit. Since the depth of a connection hole for connecting the semiconductor substrate and the conductive layers located above the gate electrode can be made shallow, an excellent covering condition inside the connection hole can be obtained in the conductive layers. Consequently, poor electric connection of the conductive layers can be prevented in the connection hole, thus improving the reliability of the semiconductor storage unit.
In the semiconductor storage unit described above, it is preferable that the bit line and the surface of the semiconductor substrate are connected through a connection hole that is formed by making an opening in the insulating film and that opens between the bit line and the surface of the semiconductor substrate, and the charge-storage electrode and the surface of the semiconductor substrate are connected through a connection hole that is formed by making an opening in the insulating film and that opens between the charge-storage electrode and the surface of the semiconductor substrate.
It is preferable that an insulating film is formed between a bottom face of the opening and the gate electrode.
Further, it is preferable that a plate electrode of a conductive film is formed on the charge-storage electrode and the insulating film via a capacity insulating film.
It is also preferable that the bit line is formed between the semiconductor substrate and the plate electrode.
It is preferable that the bit line is formed on the plate electrode via an insulating film.
It is further preferable that the connection hole for connecting the bit line and the semiconductor substrate passes through between the adjacent plate electrodes. According to the semiconductor storage unit described above, the connection hole is secured within a pattern of the plate electrode, thus enabling the semiconductor storage unit to be highly integrated.
It is preferable that the depth of the opening is deeper than that of the impurity-diffusion layer. According to the semiconductor storage unit described above, reliable insulation can be obtained between memory cells having a switching transistor provided with a gate electrode within the semiconductor substrate.
It is also preferable that the openings described above include openings in which the gate electrode is formed and openings in which the gate electrode is not formed, and in the openings in which the gate electrode is formed, besides the impurity-diffusion layer described above, a second impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate is formed.
It is preferable that an impurity-diffusion layer having the same conductive type as that of the semiconductor substrate is formed in the openings in which the gate electrode is formed and isolates the second impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate formed besides the former impurity-diffusion layer. According to the semiconductor storage unit described above, threshold voltage control of a switching transistor of a memory cell can be performed securely. That is to say, even in the case of miniaturizing a semiconductor storage unit, when the impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate is isolated by the impurity-diffusion layer having the same conductive type as that of the semiconductor substrate and these isolated impurity-diffusion layers are used as a source and a drain, the on-off control of the switching transistor can be performed at the gate electrodes.
It is further preferable that the depth of the impurity-diffusion layer having the same conductive type as that of the semiconductor substrate is deeper than that of the second impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate. According to the semiconductor storage unit described above, the impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate can be isolated securely by the impurity-diffusion layer having the same conductive type as that of the semiconductor substrate.
It is preferable that the two impurity-diffusion layers having a reverse conductive type as compared to that of the semiconductor substrate described above are a source and a drain of a switching transistor of a memory cell, the gate electrode is a gate electrode of the switching transistor of a memory cell, and the insulating filed-in layer formed at the opening having no gate electrode is an element-isolation region. According to the semiconductor storage unit described above, the depth of the connection hole for connecting the bit line and the semiconductor substrate and the depth of the connection hole for connecting the charge-storage electrode and the semiconductor substrate are shallow. Therefore, an excellent condition for covering the materials of the bit line and the charge-storage electrode can be obtained inside the connection holes and poor electric connection inside the connection holes can be prevented, thus improving the reliability of the semiconductor storage unit.
A method of manufacturing a semiconductor storage unit of the present invention comprises: forming a first impurity-diffusion layer on a semiconductor substrate, the first impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate; forming a first insulating film on the semiconductor substrate and then a plurality of first openings with a groove shape by partially removing the first insulating film and the semiconductor substrate by photoetching; forming a filled-in layer in the first openings by depositing a second insulating film on the semiconductor substrate; flattening the first and second insulating films on the semiconductor substrate; forming second openings by partially removing the filled-in layer in specific first openings selected from the plurality of first openings by photoetching; depositing a third insulating film in the second openings and a first conductive film on the semiconductor substrate sequentially; and forming a gate electrode within the second opening via the third insulating film by leaving the first conductive film in the second openings.
According to the method of manufacturing a semiconductor storage unit described above, the gate electrode is formed within the semiconductor substrate. Therefore, the short circuit between the gate electrode and the other conductive layers does not occur easily. Since there is no difference in level corresponding to the film thickness of the gate electrode on the surface of the semiconductor substrate after forming the gate electrodes, i.e. the surface of the semiconductor substrate is almost flat, the deposited film thickness of the insulating film on the gate electrode can be made thinner. Consequently, the depth of the connection hole for connecting the semiconductor substrate and the conductive layers located above the gate electrode can be made shallower and an excellent covering condition inside the connection hole can be obtained in the conductive layers. Therefore, poor electric connection of the conductive layers in the connection hole can be prevented, and thus a highly reliable semiconductor storage unit can be manufactured easily. In addition, a switching transistor region of a memory cell and an isolation region between memory cells are formed simultaneously, thus reducing the number of manufacturing processes and manufacturing costs.
It is preferable that after forming the gate electrode the method further comprises: depositing a fourth insulating film on the semiconductor substrate, flattening the fourth insulating film, and then forming a first connection hole in the fourth insulating film by photoetching, with the first connection hole reaching the surface of the semiconductor substrate; depositing a second conductive film on the semiconductor substrate and then forming a bit line by photoetching; depositing a fifth insulating film on the semiconductor substrate, flattening the fifth insulating film and then forming a second connection hole in the fifth insulating film by photoetching, with the second connection hole reaching the surface of the semiconductor substrate; and depositing a third conductive film on the semiconductor substrate and then forming a charge-storage electrode by photoetching.
It is also preferable that after forming the charge-storage electrode, he method further comprises depositing a capacity insulating film and a fourth conductive film sequentially and then forming a plate electrode by photoetching.
It is further preferable that the first openings are formed using a mask pattern formed by combining two figures that are not in contact with each other in an active region of a unit memory cell. According to the method of manufacturing a semiconductor storage unit described above, it is possible to specify the isolation region between the memory cells and the impurity-diffusion layer region simultaneously, thus reducing the number of manufacturing processes and manufacturing costs.
It is preferable that the first openings are formed using a mask pattern formed by combining two congruent figures that are not in contact with each other in an active region of a unit memory cell. According to the method of manufacturing a semiconductor storage unit described above, the isolation region between the memory cells and the impurity-diffusion layer region can be specified simultaneously, thus reducing the number of manufacturing processes and manufacturing costs. Furthermore, since the mask pattern is formed by combining two congruent figures, the memory cell region can be made smaller than that in the case where the two figures are not congruent. This enables higher integration.
It is preferable that after forming the gate electrode the method described above further comprises: depositing a fourth insulating film on the semiconductor substrate, flattening the fourth insulating film, and then forming a first connection hole in the fourth insulating film by photoetching, with the first connection hole reaching the surface of the semiconductor substrate; depositing a second conductive film on the semiconductor substrate and then forming a charge-storage electrode by photoetching; depositing a capacity insulating film and a third conductive film on the semiconductor substrate and then forming a plate electrode by photoetching; depositing a fifth insulating film on the semiconductor substrate, flattening the fifth insulating film, and then forming a second connection hole in the fifth insulating film by photoetching, with the second connection hole reaching the surface of the semiconductor substrate; and depositing a fourth conductive film on the semiconductor substrate and then forming a bit line by photoetching.
It is further preferable that the method described above further comprises: after forming the first openings and before forming the filled-in layer, forming a second impurity-diffusion layer having a reverse conductive type as compared to that of the semiconductor substrate in the first openings.
It is preferable that the method described above further comprises: after forming the second openings and before forming the third insulating film, forming a third impurity-diffusion layer having the same conductive type as that of the semiconductor substrate in the first openings, with the third impurity-diffusion layer isolating the second impurity-diffusion layer. As described above, the formation of the third impurity-diffusion layer enables reliable threshold voltage control of a switching transistor of a memory cell. That is to say, even in the case of miniaturizing a semiconductor storage unit, when the second impurity-diffusion layer is isolated by the third impurity-diffusion layer and these isolated impurity-diffusion layers are used as a source and a drain, the on-off control of the switching transistor can be performed at the gate electrodes.
It is preferable that the depth of the third impurity-diffusion layer is deeper than that of the second impurity-diffusion layer. According to the method of manufacturing a semiconductor storage unit as described above, the second impurity-diffusion layer can be isolated by the third impurity-diffusion layer securely.
It is preferable that the second impurity-diffusion layers are formed by ion implantation at an implantation angle of less than 90xc2x0 with respective to the surface of the semiconductor substrate.
According to the method of manufacturing a semiconductor storage unit described above, the impurity-diffusion layer in a memory cell is formed within the first openings. Consequently, a memory cell switching transistor provided with the gate electrode within the semiconductor substrate can be formed.
Further, it is preferable that the depth of the first opening is deeper than that of the first impurity-diffusion layer.
According to the method of manufacturing a semiconductor storage unit described above, the impurity-diffusion layer region forming the switching transistor and the region where the gate electrode is provided are specified within the semiconductor substrate. At the same time, the conductive layers in the element-isolation region are removed. Consequently, a highly reliable semiconductor storage unit can be manufactured.
It is further preferable that the second openings are formed so that the depth of the second opening measured from the surface of the semiconductor substrate is equal to or deeper than that of the first opening measured from the surface of the semiconductor substrate and is shallower than that of the second impurity-diffusion layer at the bottom of the second opening measured from the surface of the semiconductor substrate.
According to the method of manufacturing a semiconductor storage unit described above, the region where the gate electrode is provided and the region where the gate electrode is insulated from the other conductive layers are specified within the semiconductor substrate simultaneously, thus reducing the number of manufacturing processes and manufacturing costs.